We designed the following two versions of the evaluation ecg patch with the components mentioned along with it. Both of these were placed on the SPI header on the firefly node.
(a) The minimal version had just the ADC (which needs a crystal and a few capacitors) and it looked like the following
(b) The full fledged version had the whole circuit implemented.
The following were the pin configuration changes made on firefly board:-
ADC Data ready PIN was mapped to PORT E PIN4
ADC Chip Select PIN was mapped to PORT E PIN5
We wrote the ADC driver on top of the SPI driver on nano-RK. The adc driver had the following characteristics:-
(a) ADC clock configured to 100 Hz
(b) the ADC data was read by the nano-RK task at 10 ms
(c) Data was collected in a buffer and sent to the UART simultaneously.
Problem that we go stuck up for a long time: Using ADC and Radio at the same time. When we used bmac APIs along with our ADC driver in our task, it just wouldnt work!! We think the problem is because of simultaneously using SPI for both the functionalities
(a) The minimal version had just the ADC (which needs a crystal and a few capacitors) and it looked like the following
(b) The full fledged version had the whole circuit implemented.
The following were the pin configuration changes made on firefly board:-
ADC Data ready PIN was mapped to PORT E PIN4
ADC Chip Select PIN was mapped to PORT E PIN5
We wrote the ADC driver on top of the SPI driver on nano-RK. The adc driver had the following characteristics:-
(a) ADC clock configured to 100 Hz
(b) the ADC data was read by the nano-RK task at 10 ms
(c) Data was collected in a buffer and sent to the UART simultaneously.
Problem that we go stuck up for a long time: Using ADC and Radio at the same time. When we used bmac APIs along with our ADC driver in our task, it just wouldnt work!! We think the problem is because of simultaneously using SPI for both the functionalities
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