The software front

The ADC driver and data transmission

 The ADC was configured to have the following characteristics
(1) ADC clock configured for 100 Hz sample rate
(2) Setting CPHA and CPOL both to 1
(3) ADC data is read from a thread that runs every 10 milliseconds
(4) we do a non-blocking wait for 8 milliseconds and a busy wait after that till the data is available.
Additionally, our ADC chip (AD7705) requires clock polarity (CPOL) and clock phase (CPHA) both set to 1 where as the radio chip (Chipcon CC2420) requires both of these bits set to 0. This necessitates a 'switch' between the two configurations when trying to talk to each one of them. We used enable ADC and disable ADC APIs in order to accomplish the same.

The MATLAB Code

MATLAB algorithm was developed to read in the real-time incoming data, as it came through the serial port, and employ digital signal processing techniques to achieve a coherent display of data. While using three nodes, the MATLAB function sorted through the incoming data by arranging the packets received by their associated node ID. Each node was assigned an identification number and was placed into a data vector exclusive to that node. 

A real time high pass filter was implemented to resolve drifts in the signal and retain a steady output from the leads. A cutoff frequency of 80 Hz was selected for the high pass filter.